POWER STAGE / SYNCHRONOUS BUCK

Easy Buck Converter Calculator

Change an input to update the operating point and ripple plots.

Summary Range & compare Quick theory

01 Circuit & Operating ConditionsIdeal switches · CCM model

Input Supply VIN

Input voltage

DC supply

MOSFET QHS / QLS

Ideal switches

Enable RDS(on) & DCR above to include resistance.

Inductor Auto L

Inductance Calculated

µH

Current ripple target

ΔIL — A pp

Output Voltage VOUT

Output voltage

Output power — W

Output Capacitor Auto C

Effective capacitance Calculated

µF

Voltage ripple target

mV pp

ESR

mΩ

Use effective C after DC bias derating.

Load IOUT

Average load current

Equivalent load — Ω

Controller

PWM Controller

Switching Frequency

Duty Auto

tON — ns

Current ripple ΔIL——

Output ripple ΔVOUT——

Inductor peak / RMS——

LC resonant frequency——

Inductor Current

iL(t)

Output Voltage Ripple

vOUT(t) − VOUT

02 / DESIGN EXPLORER

Operating Range & Design Comparison

Read the quick guide

See how the same L and C behave across input voltage and load.

Minimum Input Voltage

Maximum Input Voltage

Minimum Load Current

Maximum Load Current

Datasheet limits (optional)

Inductor saturation current

Inductor thermal RMS rating

Controller minimum on-time

Use ratings at your worst operating temperature and conditions. Blank limits are unchecked. Saturation and thermal ratings are different.

The range calculation freezes L, effective C, frequency and resistance from above. It recalculates duty to hold the current VOUT, even in Duty input mode. Sampling does not prove the worst case over a continuous range or simulate control-loop response.

A / B Design Comparison

Save A, then change the calculator inputs to compare with current design B. A is kept only until this page closes or reloads.

03 / BUCK DESIGN NOTES

Buck Theory · In Design Order

Start with voltage and frequency, then L/current ripple, C/voltage ripple, and finally component limits and operating range. Equations below assume ideal CCM.

Duty · The conversion ratio

D = VOUT / VIN · tON = D / fSW

Inductor current rises during HS on-time and falls during the LS interval.
At fixed output, a higher VIN reduces duty and on-time.
An on-time below the IC minimum may prevent regulation at that frequency.

L · Set the current ripple

ΔIL = (VIN − VOUT) · D / (L · fSW)

At a fixed operating point, larger L reduces ripple and peak current.
Auto L uses your ripple target. The 30% default is a starting point; follow the IC recommendations.
After selecting a part, disable Auto L and enter its L and DCR.

C and ESR · Two ripple terms

ΔVC = ΔIL / (8 · fSW · C) · ΔVESR = ΔIL · ESR

More C reduces charge/discharge ripple; the ESR term remains.
Enter effective capacitance at the operating voltage and temperature.
Auto C uses the sum of ripple bounds; displayed ripple comes from the combined waveform.

Peak and RMS · Component limits

IL,peak = IOUT + ΔIL / 2 · IL,RMS = √(IOUT² + ΔIL² / 12)

Use peak current to check inductor saturation and IC current limits.
Use RMS current for heating and copper loss; the ratings are not interchangeable.
Equality leaves no margin. Review temperature, tolerances and transient current too.

CCM and reverse current · Light load

IOUT,boundary = ΔIL / 2

The CCM boundary occurs when minimum inductor current reaches zero.
Forced CCM permits negative current. DCM points in diode-emulation mode are unsupported.
Reducing load can cross the boundary. Include light-load points in your range check.

After calculation · Check the datasheet

L / C / ESR / RDS(on) / tON

Ideal equations describe the steady-state power stage; resistance mode uses mean voltage drops.
LC resonance alone does not establish control-loop stability.
Separately check recommended L/C, input capacitors, losses, thermal behavior, layout and load transients.

References & further readingTI · Buck power stage TI · Minimum on/off time ADI · LTpowerCAD

Equations, Model Limits & Details

Calculation Details

Model & Assumptions

The base model is an ideal single-phase buck converter in steady-state CCM. With RDS(on) and DCR enabled, the mean load-current voltage drop determines duty cycle or VOUT, and ripple is approximated as triangular at that operating point. Exact exponential current caused by resistance is not calculated.

VOUT ≈ D·VIN − IOUT·[D·RHS + (1−D)·RLS + DCR]

Auto L sizes the inductor from the current ripple target. Auto C conservatively sizes the minimum effective capacitance so that ΔVC,pp + ΔVESR,pp stays within the voltage ripple target. Displayed ripple is the peak-to-peak value of the combined capacitor and ESR voltage waveform.

Component tolerances, temperature variation, inductor saturation and core loss, ESL, switching spikes, dead time, control loops and load transients are not included. These results do not determine total efficiency or stability.

TI · Buck Power Stage Calculations ↗ TI · MOSFET Loss Calculations ↗

Design Summary

—

Inductance——

Effective capacitance——

Duty / fSW—

ΔIL / ΔVOUT—

Values use a steady-state CCM approximation. Check standard component values, tolerances and ratings.

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